1. Field of the Invention
The present invention relates to a diode such as a diode used in a reference potential generating circuit for a DRAM.
2. Description of the Related Art
A conventional reference potential generating circuit for a DRAM comprises a diode having an arrangement as shown in FIG. 1. More specifically, in a major surface region of an n-type silicon substrate 1, a p-type diffusion layer 2 containing boron ions as a p-type impurity is formed. The p-type diffusion layer 2 has a depth of e.g., about 0.3 .mu.m from the major surface 1 of the substrate 1, and an impurity concentration of 10.sup.19 atoms.multidot.cm.sup.-3 or more. In the p-type diffusion layer 2, an n-type diffusion layer 3 containing arsenic ions as an n-type impurity is formed. The n-type diffusion layer 3 has a depth of e.g., about 0.2 .mu.m from the major surface of the substrate 1, and an impurity concentration of 10.sup.19 atoms.multidot.cm.sup.-3 or more (in general, since the diffusion layer 3 is formed by doping an impurity in the diffusion layer 2, the diffusion layer 3 has a higher impurity concentration than that of diffusion layer 2). On the silicon substrate 1, an insulating film 4 is formed. The insulating film 4 has a thickness of about 1 to 2 .mu.m. A first contact hole 5 is formed in the insulating film 4 at a position corresponding to the n-type diffusion layer 3. A second contact hole 6 is formed in part of a region on the p-type diffusion layer 2. In the first and second contact holes 5 and 6 and on parts of a region on the insulating film 4 around the contact holes 5 and 6, wiring patterns 7A and 7B consisting of e.g., aluminum are formed to be in contact with the p-type diffusion layer 2 and the n-type diffusion layer 3, respectively.
In a diode having such a structure, a voltage, a so-called forward dropping voltage VF, is generated between p-type silicon and n-type silicon when a forward current flows between the wiring patterns 7A and 7B respectively contacting the p-type diffusion layer 2 and the n-type diffusion layer 3. The voltage VF depends on impurity concentrations of p-type silicon and n-type silicon i.e., the p-type diffusion layer 2 and the n-type diffusion layer 3, and has less temperature dependency. In this aspect, the voltage VF generated by the diode is suitable for generating a reference potential, and is used in a reference potential generating circuit for a DRAM or the like.
Recently, higher integration of many types of semiconductor devices such as a DRAM has been achieved. As higher integration or element micropatterning is achieved, a diffusion layer having a small depth from the major surface of the substrate 1 and a high impurity concentration is required. As a result, with the development of element micropatterning, a p-n junction having a small diffusion depth and a high impurity concentration is formed inside the semiconductor device. The diode described above also has this tendency. The diffusion depth of the p-type diffusion layer 2 from the major surface of the substrate 1 is about 0.3 .mu.m, and that of the n-type diffusion layer 3 is about 0.2 .mu.m. The impurity concentrations of these two diffusion layers are 10.sup.19 atoms.multidot.cm.sup.-3 or more. When the n-type diffusion layer 3 is formed in the shallow p-type diffusion layer 2, a shallow p-n junction is formed. When the shallow p-n junction is formed, erosion of silicon by a wiring material e.g., aluminum, constituting the wiring patterns 7A and 7B, a so-called aluminum spike becomes a serious problem. An aluminum spike is a phenomenon wherein aluminum reacts with silicon and aluminum punches through a diffusion layer to reach a substrate. When the aluminum spike occurs in a diode as shown in FIG. 1, aluminum constituting the wiring pattern 7B punches through the n-type diffusion layer 3, and reaches the p-type diffusion layer 2 to cause a short circuit. To avoid this problem, the p-type diffusion layer 2 must be formed so as to have enough depth from the major surface of the substrate 1. However, a deep diffusion layer makes higher integration or element micropatterning difficult.
On the other hand, in formation of an element structure, such as the diode described above, that is, a p-n junction structure having an n-type diffusion layer in a p-type diffusion layer, a difference between diffusion lengths caused by a difference of diffusion coefficients between boron as a p-type impurity and arsenic as an n-type impurity is utilized. In general, the diffusion coefficient of boron is higher than that of arsenic. Therefore, after boron ions and arsenic ions are implanted in the major surface region of the substrate 1, both ions are simultaneously thermally diffused to form the p-type diffusion layer 2 and the n-type diffusion layer 3. A temperature or a time period of thermal diffusion is set depending on design dimensions of the p-type diffusion layer 2. Therefore, it is not preferable to form the n-type diffusion layer 3 having a small depth from the substrate 1 or a high impurity concentration. As a result, satisfactory element micropatterning cannot be performed.